Efficient H.264 Decoder Architecture using External Memory and Pipelining
نویسندگان
چکیده
منابع مشابه
High-Throughput and Memory Efficient LDPC Decoder Architecture
Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents a new kind of high-throughput and memory efficient LDPC decoder architecture. In general, more than fifty percent of memory can be saved over conven...
متن کاملEfficient associative memory using small-world architecture
Most models of neural associative memory have used networks with broad connectivity. However, from both a neurobiological viewpoint and an implementation perspective, it is logical to minimize the length of inter-neural connections and consider networks whose connectivity is predominantly local. The `small-world networksa model described recently by Watts and Strogatz provides an interesting ap...
متن کاملArea-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division
In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the IEEE 802.16e WiMAX standard. The decoder supports all the code rates and codeword lengths defined in the standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest com...
متن کاملPower- and Area-efficient Single Siso Architecture of Turbo Decoder
In this paper, we propose a powerand area-efficient architecture of Turbo decoder. In order to improve the nonfunctional performance metrics such as power consumption and area, we use the trade-off method between bit error rate (BER) performance and the two non-functional performance metrics. Our proposed architecture shows about 16.7% reduction in power consumption and about 22.5% reduction in...
متن کاملEfficient Support for Pipelining in Distributed Shared Memory Systems∗
Though more difficult to program, distributed-memory parallel machines provide greater scalability than their shared-memory counterparts. Distributed Shared Memory (DSM) systems provide the abstraction of shared memory on a distributed machine. While DSMs provide an attractive programming model, they currently can not efficiently support all classes of scientific applications. One such class ar...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Indonesian Journal of Electrical Engineering and Computer Science
سال: 2018
ISSN: 2502-4760,2502-4752
DOI: 10.11591/ijeecs.v12.i3.pp995-1002